FPGA Verification Engineer - UVM (Hybrid)
Nesco Resource ·nescoresource.com
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Description:
The selected candidate will be responsible for ASIC & FPGA development on R&D program. This engineer with have experience in developing, testing, and integrating digital signal processing (DSP), high speed digital design, high speed communication and system-on-chip (SOC) implemented on FPGA platforms. Experience with COTS based control platforms and embedded processors on FPGA platforms. This person will help develop more affordable ways to automate and develop scripts to improve FPGA development efforts. Cross discipline collaboration with Systems Architects, RF/Analog & Digital Circuit designers and ASIC/FPGA engineers to create leading edge products for future business growth, contributing to complex systems employing high speed networking concepts. The selected candidate will also provide support and technical direction to junior engineers. Overall contribution to design, simulation, verification, integration & test of complex, high speed products.
This is primarily a Verification Position:
Experienced FPGA Verification Engineer to support the development and certification of safety critical avionics hardware. The engineer will support verification activities required for DO 254 compliance, including requirement analysis, test development, execution, simulation, coverage analysis, and back annotation of results. The role will work closely with design, systems, and certification teams to ensure the FPGA design meets stringent DO-254 Level A standards.
- Experience with FPGA design tools (Xilinx Vivado, Client Quartus, Synopsys Synplify).
- Proficient in SystemVerilog
- Proficiency with HDL simulators, waveform viewers, and coverage tools.
- Familiarity with hardware in the loop (HIL) test setups and test equipment (e.g., JTAG, logic analyzers).
- Prior involvement in FAA or EASA certification audits.
- Experience with version control systems and configuration management.
Desired Skills: Proficient in UVM. Proficient in C.
Nesco Resource offers a comprehensive benefits package for our associates, which includes a MEC (Minimum Essential Coverage) plan that encompasses Medical, Vision, Dental, 401K, and EAP (Employee Assistance Program) services.
Nesco Resource provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws.
The selected candidate will be responsible for ASIC & FPGA development on R&D program. This engineer with have experience in developing, testing, and integrating digital signal processing (DSP), high speed digital design, high speed communication and system-on-chip (SOC) implemented on FPGA platforms. Experience with COTS based control platforms and embedded processors on FPGA platforms. This person will help develop more affordable ways to automate and develop scripts to improve FPGA development efforts. Cross discipline collaboration with Systems Architects, RF/Analog & Digital Circuit designers and ASIC/FPGA engineers to create leading edge products for future business growth, contributing to complex systems employing high speed networking concepts. The selected candidate will also provide support and technical direction to junior engineers. Overall contribution to design, simulation, verification, integration & test of complex, high speed products.
This is primarily a Verification Position:
Experienced FPGA Verification Engineer to support the development and certification of safety critical avionics hardware. The engineer will support verification activities required for DO 254 compliance, including requirement analysis, test development, execution, simulation, coverage analysis, and back annotation of results. The role will work closely with design, systems, and certification teams to ensure the FPGA design meets stringent DO-254 Level A standards.
- Experience with FPGA design tools (Xilinx Vivado, Client Quartus, Synopsys Synplify).
- Proficient in SystemVerilog
- Proficiency with HDL simulators, waveform viewers, and coverage tools.
- Familiarity with hardware in the loop (HIL) test setups and test equipment (e.g., JTAG, logic analyzers).
- Prior involvement in FAA or EASA certification audits.
- Experience with version control systems and configuration management.
Desired Skills: Proficient in UVM. Proficient in C.
Nesco Resource offers a comprehensive benefits package for our associates, which includes a MEC (Minimum Essential Coverage) plan that encompasses Medical, Vision, Dental, 401K, and EAP (Employee Assistance Program) services.
Nesco Resource provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws.
Frequently asked questions
Who is hiring for the FPGA Verification Engineer - UVM (Hybrid) role?
Nesco Resource is hiring for the FPGA Verification Engineer - UVM (Hybrid) position, a Shazamme client. Apply directly on the employer's career site.
Where is the FPGA Verification Engineer - UVM (Hybrid) job located?
The FPGA Verification Engineer - UVM (Hybrid) role with Nesco Resource is based in Owego, NY, US. The role is hybrid-friendly.
Is the FPGA Verification Engineer - UVM (Hybrid) role remote?
Yes — the FPGA Verification Engineer - UVM (Hybrid) position at Nesco Resource is hybrid. Candidates based in US are preferred.
What does the FPGA Verification Engineer - UVM (Hybrid) role pay?
Nesco Resource lists the FPGA Verification Engineer - UVM (Hybrid) role at USD 60–80 per hour.
Is the FPGA Verification Engineer - UVM (Hybrid) role full-time or contract?
This is a full time position at Nesco Resource.
What experience level is the FPGA Verification Engineer - UVM (Hybrid) role?
The FPGA Verification Engineer - UVM (Hybrid) position is aimed at mid-level candidates.
How do I apply for the FPGA Verification Engineer - UVM (Hybrid) role at Nesco Resource?
Apply directly on Nesco Resource's career page via the Apply button on this listing. ZammeJobs links straight through to the employer's ATS — no third-party form, no resume database.