FPGA Design/Verification Engineer
Nesco Resource ·nescoresource.com
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Description:
The selected candidate will be responsible for ASIC & FPGA verification utilizing UVM.
Key activities you will accomplish in this role:
• Support other aspects of ASIC and FPGA development such as architecture, design, analysis, and test.
• Support technical reviews and be able to present to internal and external customers
• Devise a unique verification plan for a given design.
• Use SystemVerilog and Universal Verification Methodology (UVM) to verify a design in a Linux-based high-performance computing environment.
• Document verification plan and results.
• Work with an independent verification team to resolve bugs found in the design.
To be effective in this role, you will need:
• ASIC/FPGA verification experience with modern verification methodologies such as UVM, OVM or VMM.
• 3 years professional experience.
• Active DoD Secret clearance
Work Schedule
5/40-1st Shift
Security Clearance Comments
Active DoD Secret - NGI-HQ085621-C-0001
Nesco Resource offers a comprehensive benefits package for our associates, which includes a MEC (Minimum Essential Coverage) plan that encompasses Medical, Vision, Dental, 401K, and EAP (Employee Assistance Program) services.
Nesco Resource provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws.
The selected candidate will be responsible for ASIC & FPGA verification utilizing UVM.
Key activities you will accomplish in this role:
• Support other aspects of ASIC and FPGA development such as architecture, design, analysis, and test.
• Support technical reviews and be able to present to internal and external customers
• Devise a unique verification plan for a given design.
• Use SystemVerilog and Universal Verification Methodology (UVM) to verify a design in a Linux-based high-performance computing environment.
• Document verification plan and results.
• Work with an independent verification team to resolve bugs found in the design.
To be effective in this role, you will need:
• ASIC/FPGA verification experience with modern verification methodologies such as UVM, OVM or VMM.
• 3 years professional experience.
• Active DoD Secret clearance
Work Schedule
5/40-1st Shift
Security Clearance Comments
Active DoD Secret - NGI-HQ085621-C-0001
Nesco Resource offers a comprehensive benefits package for our associates, which includes a MEC (Minimum Essential Coverage) plan that encompasses Medical, Vision, Dental, 401K, and EAP (Employee Assistance Program) services.
Nesco Resource provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws.
Frequently asked questions
Who is hiring for the FPGA Design/Verification Engineer role?
Nesco Resource is hiring for the FPGA Design/Verification Engineer position, a Shazamme client. Apply directly on the employer's career site.
Where is the FPGA Design/Verification Engineer job located?
The FPGA Design/Verification Engineer role with Nesco Resource is based in Littleton, CO, US. The role is onsite-friendly.
Is the FPGA Design/Verification Engineer role remote?
Yes — the FPGA Design/Verification Engineer position at Nesco Resource is onsite. Candidates based in US are preferred.
What does the FPGA Design/Verification Engineer role pay?
Nesco Resource lists the FPGA Design/Verification Engineer role at USD 80–100 per hour.
Is the FPGA Design/Verification Engineer role full-time or contract?
This is a full time position at Nesco Resource.
What experience level is the FPGA Design/Verification Engineer role?
The FPGA Design/Verification Engineer position is aimed at mid-level candidates.
How do I apply for the FPGA Design/Verification Engineer role at Nesco Resource?
Apply directly on Nesco Resource's career page via the Apply button on this listing. ZammeJobs links straight through to the employer's ATS — no third-party form, no resume database.