FPGA Verification Engineer - UVM (Secret Clearance)
Nesco Resource ·nescoresource.com
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Description:
The selected candidate will be responsible for ASIC & FPGA verification on R&D program. This engineer will be a verification UVM expert.
This engineer with have experience :
-Verifying FPGA and/or ASIC designs including creating UVM verification environments, testbenches, tests and coverage.
-Developing and finding more affordable ways to automate and develop verification scripts to improve FPGA verification efforts.
Cross discipline collaboration with RTL Designers, Systems Architects, RF/Analog & Digital Circuit designers and ASIC/FPGA engineers to create leading edge products for future business growth, contributing to complex systems employing high speed networking concepts.
The selected candidate will also provide support and technical direction to junior engineers.
Overall contribution to simulation, verification, integration & test of complex, high speed products.
Preferred : onsite Sunnyvale, CA. Possible : onsite Denver CO. Will consider remote for the right candidate.
Nesco Resource offers a comprehensive benefits package for our associates, which includes a MEC (Minimum Essential Coverage) plan that encompasses Medical, Vision, Dental, 401K, and EAP (Employee Assistance Program) services.
Nesco Resource provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws.
The selected candidate will be responsible for ASIC & FPGA verification on R&D program. This engineer will be a verification UVM expert.
This engineer with have experience :
-Verifying FPGA and/or ASIC designs including creating UVM verification environments, testbenches, tests and coverage.
-Developing and finding more affordable ways to automate and develop verification scripts to improve FPGA verification efforts.
Cross discipline collaboration with RTL Designers, Systems Architects, RF/Analog & Digital Circuit designers and ASIC/FPGA engineers to create leading edge products for future business growth, contributing to complex systems employing high speed networking concepts.
The selected candidate will also provide support and technical direction to junior engineers.
Overall contribution to simulation, verification, integration & test of complex, high speed products.
Preferred : onsite Sunnyvale, CA. Possible : onsite Denver CO. Will consider remote for the right candidate.
Nesco Resource offers a comprehensive benefits package for our associates, which includes a MEC (Minimum Essential Coverage) plan that encompasses Medical, Vision, Dental, 401K, and EAP (Employee Assistance Program) services.
Nesco Resource provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws.
Frequently asked questions
Who is hiring for the FPGA Verification Engineer - UVM (Secret Clearance) role?
Nesco Resource is hiring for the FPGA Verification Engineer - UVM (Secret Clearance) position, a Shazamme client. Apply directly on the employer's career site.
Where is the FPGA Verification Engineer - UVM (Secret Clearance) job located?
The FPGA Verification Engineer - UVM (Secret Clearance) role with Nesco Resource is based in Sunnyvale, CA, US. The role is remote-friendly.
Is the FPGA Verification Engineer - UVM (Secret Clearance) role remote?
Yes — the FPGA Verification Engineer - UVM (Secret Clearance) position at Nesco Resource is remote. Candidates based in US are preferred.
What does the FPGA Verification Engineer - UVM (Secret Clearance) role pay?
Nesco Resource lists the FPGA Verification Engineer - UVM (Secret Clearance) role at up to USD 100 per hour.
Is the FPGA Verification Engineer - UVM (Secret Clearance) role full-time or contract?
This is a full time position at Nesco Resource.
What experience level is the FPGA Verification Engineer - UVM (Secret Clearance) role?
The FPGA Verification Engineer - UVM (Secret Clearance) position is aimed at mid-level candidates.
How do I apply for the FPGA Verification Engineer - UVM (Secret Clearance) role at Nesco Resource?
Apply directly on Nesco Resource's career page via the Apply button on this listing. ZammeJobs links straight through to the employer's ATS — no third-party form, no resume database.