后端 / 物理设计工程师 ASIC Backend / Physical Design Engineer

The company is a global semiconductor solutions provider delivering high-performance custom ASIC chip design. They are seeking an experienced Senior ASIC Backend / Physical Design Engineer to join the Hong Kong team (visa sponsorship available). This role will lead full-chip physical implementation on advanced process nodes, contributing to cutting-edge projects such as AI accelerators and automotive vision processors.

We are seeking an experienced ASIC Backend / Physical Design Engineer to join a high-performing semiconductor team working on advanced, large-scale chip designs. This role focuses on full-chip backend implementation, covering P&R, timing closure, physical verification, and signoff.

Key Responsibilities

• Drive full-chip physical design implementation from netlist to GDS, including:
  • Place & Route (P&R)
  • Timing closure (STA)
  • Power and IR drop analysis
  • Physical verification (DRC/LVS)
• Perform top-level integration and full-chip signoff activities
• Conduct deep analysis and debugging of backend issues (timing, congestion, IR drop, etc.)
• Optimize design for performance, power, and area (PPA)
• Collaborate cross-functionally with frontend, synthesis, and system teams
• Support ECO implementation and design iterations
• Develop and maintain automation scripts to improve flow efficiency

Key Requirements

• Solid experience in ASIC physical design / backend engineering
• Strong hands-on experience with:
  • Cadence Innovus or SNPS Fusion Complier
• Proven track record in large/advanced node, full-chip projects*(Block-level experience alone is not sufficient)*
• Part of top-level job experiences is essential, e.g., whole chip power analysis experiences, whole chip physical validation experiences, whole chip STA experiences.
• Demonstrated ability in debugging and problem-solving, beyond just running standard flows
• Good scripting skills (Tcl, Python, or Shell)

该公司是全球的半導體解決方案供應商,提供高性能定制 ASIC 芯片設計。尋找一位經驗豐富的高級後端物理設計工程師,加入香港團隊（提供簽證）。將負責先進制程節點下的全芯片物理實現,參與 AI 加速器、汽車視覺處理器等前沿項目。

主要职责

• 负责从 netlist 到 GDS 的全芯片物理设计实现，包括：
  • 布局与布线（Place & Route, P&R）
  • 时序收敛（Static Timing Analysis, STA）
  • 功耗及 IR Drop 分析
  • 物理验证（DRC / LVS）
• 执行芯片顶层整合及全芯片签核（signoff）工作
• 对后端相关问题进行深入分析与调试（如时序、拥塞、IR Drop 等）
• 进行设计优化，以提升性能、功耗及面积（PPA）
• 与前端、综合（synthesis）及系统团队进行跨团队协作
• 支持ECO（工程变更）实现及设计迭代
• 开发及维护自动化脚本以提升设计流程效率

任职要求

• 具备扎实的ASIC 物理设计 / 后端工程经验
• 熟练使用以下工具之一：
  • Cadence Innovus OR SNPS Fusion Complier
• 具备先进制程或大规模全芯片项目经验*(仅有 block-level 经验无法满足岗位要求)
• 有过部分top-level的工作经验，如：
• • 静态时序分析（STA）及收敛
  • 物理验证（DRC / LVS）
  • 功耗分析及 signoff 流程
• 具备优秀的问题分析与调试能力（不仅仅是执行工具流程）
• 具备良好的脚本编写能力（Tcl / Python / Shell）