Senior Machine Learning Hardware Design Consultant

Senior Machine Learning Hardware Design Consultant

Overview

Shape the core technology behind high-performance machine learning accelerator IP. As a Senior Machine Learning Hardware Design Consultant, you will design and implement specialized digital hardware that translates mathematically complex algorithms into efficient, synthesizable silicon.

This is a hands-on ASIC hardware design role—not a machine learning software position. You will own complex core logic across the design lifecycle, from microarchitecture definition and RTL development through integration, timing closure, verification support, and silicon bring-up. Working closely with architecture, verification, physical design, firmware, and hardware engineering teams, you will help optimize designs for performance, power, area, and overall Quality of Results (QOR).

Required Skills

• Strong digital hardware and logic design fundamentals
• Expert-level RTL design experience using Verilog and/or SystemVerilog
• Proven experience designing complex blocks from specification and microarchitecture through RTL implementation and integration
• Experience implementing complex algorithms or computational features in hardware
• Several years of experience working with machine learning-related hardware or algorithms
• Strong understanding of the mathematics underlying machine learning, graphics, and/or digital signal processing algorithms
• Ability to translate mathematically complex concepts into efficient, performance-sensitive hardware
• Hands-on experience with synthesis, timing constraints, timing closure, and DFT concepts
• Experience collaborating with physical design engineers to achieve timing closure
• Strong understanding of QOR and hardware optimization for power, performance, and area
• Experience designing specialized core logic rather than general peripheral or side logic
• Understanding of microarchitectural trade-offs, datapath and control logic design, and block-level optimization
• Ability to collaborate effectively across architecture, verification, physical design, firmware, and hardware engineering teams

Nice-to-Have Skills

• Direct experience designing machine learning accelerator hardware
• Experience with 3D graphics hardware
• Experience with digital signal processing hardware or algorithms
• Experience integrating blocks into larger SoCs
• Experience with Synopsys design tools
• Exposure to firmware or driver development
• Experience with other ASIC and hardware design toolsets; tool-specific experience is secondary to demonstrated design expertise

Preferred Education and Experience

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field preferred
• At least 5 years of ASIC design experience, with a strong focus on block-level RTL design and silicon development
• 10+ years of digital or hardware design experience strongly preferred
• Demonstrated success taking blocks from microarchitecture and RTL through working silicon
• Experience applying machine learning, graphics, DSP, or related algorithms to hardware implementations

Other Requirements

• Location: San Jose, CA
• Work arrangement: Onsite preferred; flexibility may be considered for exceptional candidates
• Ability to work effectively in a fast-paced, highly specialized, and performance-sensitive hardware development environment
• Availability to begin within approximately four weeks is preferred
• Two positions are available